There are several common serial communication standards currently available, including USB (Universal Serial Bus) 1.1 that provides communication speeds up to 12 Mbps (million bits per second), FireWire (IEEE 1394) that operates at 400 Mbps, and USB 2.0 that operates at a maximum of about 480 Mbps. The operational speeds of these standards have increased over time. For example, the speed of USB 2.0 is improved over that of USB 1.1 by over 40 times. State of the art optical networks used in data communications and telecommunications may operate at bit rates up to 40 Gbps (billion bits per second).
Generally, a serial communication network includes a transmitter and a receiver. The transmitter encodes or modulates a lower speed parallel data bus into a higher speed serial data stream that is then placed on a communication media. The serial data stream travels on the communication media and is then obtained from the communication media by the receiver. The serial data stream is then processed by the receiver in order to decode or recover the original data and de-serialize the resulting data into a duplicate parallel data bus.
All clock and data recovery (CDR) circuits attempt to recover the original transmitting clock despite these variations in reference frequencies or signal degradation due to jitters. A conventional CDR circuit (which is an analog circuit) attempts to recover the clock and data by utilizing a phase detector (PD) or alternatively a phase-frequency detector (PFD) to drive a charge pump followed by a loop filter and a voltage controlled oscillator (VCO) in a phase locked loop (PLL). The phase detector detects the absolute timing error between the current recovered clock and the timing of the ideal clock, and together with the charge pump, generates an error signal proportional to the size of the timing error. This error signal is filtered using a loop filter and used to drive the VCO. The conventional linear techniques use an analog PLL, which due to variations in the transition density in the incoming data and variations in the manufacturing process, have a bandwidth, tracking capability, and frequency acquisition range that is not tightly controlled.
Another type of CDR is a digital CDR based on phase interposers. A phase interpolator based clock recovery system recovers the clock by examining the sign of the phase error between the currently recovered clock and the data. If the recovered clock is too early, the clock recovery system delays the clock. If the recovered clock is too late, the clock is advanced. Accurately and quickly finding out the appropriate amount of delay or advancement is thus a key issue for the digital CDRs.